1. Field of the Invention
The invention relates to design of tests that are used in simulation of design(s) of circuits. More specifically, the invention relates to a method and an apparatus for automatically generating goals used to evaluate functional coverage in stimulus driven simulation of the circuit designs that are typically implemented in integrated circuit (IC) chips.
2. Related Art
In the design of integrated circuit (IC) chips, it is common to test IC designs by use of a testbench. A test bench in a high-level verification language (HVL) environment includes test generators that randomly generate input signals for the IC design (expressed in a hardware description language, HDL). U.S. Pat. No. 6,141,630 granted to McNamara, et al. on Oct. 31, 2000 entitled “System and method for automated design verification” is incorporated by reference herein in its entirety as background. This patent describes a coverage analysis tool (see FIG. 1 attached hereto) which monitors output data from a simulated design and identifies portions of the simulated design that remain to be tested. The coverage analysis tool updates a coverage database. A test generator is coupled to the IC design database and the coverage database. The test generator produces and sends test vectors to the test bench which exercise (i.e., test) the portions of the simulated design that the coverage analysis tool has indicated still remain untested. The simulated design includes software, expressed in a HDL language such as Verilog or VHDL which is executed within a computer to model the operational characteristics of the circuit being designed.
Values of test vectors may be generated randomly in the belief that events of interest to the user will be reached and recognized as simulation progresses over time. However, there is no guarantee that such events will in fact occur during a limited duration within which simulation is performed, or that such events will occur even if the simulation duration is infinitely long. Some prior art testbenches allow the users to manually specify constraints on signals to be input to a circuit design's simulation. Such testbenches also allow events of interest to be manually specified by the user, in the form of “goals.” User-specified goals are typically used during simulation, to measure functional coverage of the tests. Users can review the effectiveness of tests (during simulation) in covering the specified goals, and if appropriate also create values for stimulus signals (either manually or by specifying additional directives to test generators) to attempt to achieve coverage of any events that have not yet occurred (also called “holes”).
Such prior art testbenches typically require the user to manually write up constraints on input signals, e.g. as per U.S. Pat. No. 6,499,127 incorporated by reference herein in its entirety. The user may also manually write up goals for the simulation. Such goals and/or constraints may be typically written in a hardware verification language (HVL) called “SYSTEMVERILOG” which is described in, for example, a document entitled “SystemVerilog 3.1a Language Reference Manual Accellera's Extensions to Verilog®” available at http:%%www.eda.org%sv%SystemVerilog—3.1a.pdf (wherein “/” is replaced by “%”), and this document is incorporated by reference herein in its entirety as background. An alternative HVL language is called OpenVera and is used by the VERA tool available from Synopsys, Inc. For more information on OpenVERA, see the book entitled “The Art of Verification with VERA” published September 2001 by Faisal Haque, Jonathan Michelson, and Khizar Khan that is incorporated by reference herein in its entirety. This book is available for purchase at http:%%www.verificationcentral.com%. Use of OpenVERA is also described in U.S. Pat. No. 6,925,617 that is incorporated by reference herein in its entirety, as background.